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preliminary CY15B102QN cy15v102qn excelon?-auto 2-mbit (256k 8) automotive-e serial (spi) f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-19073 rev. *f revised january 25, 2018 2-mbit (256k 8) automotive-e serial (spi) f-ram features 2-mbit ferroelectric random a ccess memory (f-ram) logically organized as 256k 8 ? virtually unlimited endurance of 10 trillion (10 13 ) read/write cycles ? 121-year data retention (see data retention and endurance on page 20 ) ? nodelay? writes ? advanced high-reliability ferroelectric process fast serial peripheral interface (spi) ? up to 50 mhz frequency ? supports spi mode 0 (0, 0) and mode 3 (1, 1) sophisticated write protection scheme ? hardware protection using the write protect (wp ) pin ? software protection using writ e disable (wrdi) instruction ? software block protection for 1/4, 1/2, or entire array device id and serial number ? device id includes manufacturer id and product id ? unique id ? serial number dedicated 256-byte special sector f-ram ? dedicated special sector write and read ? stored content can survive up to 3 standard reflow soldering cycles low-power consumption ? 400 a (typ) active current at 1 mhz ? 3.7 ma (typ) active current at 40 mhz ? 2.4 a (typ) standby current ? 0.7 a (typ) deep power down mode current ? 0.1 a (typ) hibernate mode current low-voltage operation: ? cy15v102qn: v dd = 1.71 v to 1.89 v ? CY15B102QN: v dd = 1.8 v to 3.6 v automotive operating temper ature: ?40 c to +125 c aec q100 grade 1 compliant 8-pin small outline integr ated circuit (soic) package restriction of hazardous substances (rohs) compliant functional description the excelon-auto cy15x102qn is an automotive grade, 2-mbit nonvolatile memory employin g an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads a nd writes similar to a ram. it provides reliable data retention for 121 years while eliminating the complexities, overhead, and system-level reliability problems caused by serial flash, eeprom, and other nonvolatile memories. unlike serial flash and eepr om, the cy15x102qn performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial write endurance compared to other nonvolatile memories. the cy15x102qn is capable of supporting 10 13 read/write cycles, or 10 million times more write cycles than eeprom. these capabilities make the cy15x102qn ideal for nonvolatile memory applications, requirin g frequent or rapid writes. examples range from data collecti on, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or eeprom can cause data loss. the cy15x102qn provides subs tantial benefits to users of serial eeprom or flash as a hardware drop-in replacement. the cy15x102qn uses the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. the device incorporates a read-only device id and unique id features, which allow the host to determ ine the manufacturer, product density, product revision, and unique id for each part. the device also provides a writable, 8-byte serial number registers, which can be used to identify a specific board or a system. the device specifications are guaranteed ov er an automotive operating temperature range of ?40 c to +125 c. errata: for information on silicon errata, see ?errata? on page 29. details include trigger conditions, devices affected, and proposed workaround.
document number: 002-19073 rev. *f page 2 of 32 preliminary CY15B102QN cy15v102qn logic block diagram si so wp reset cs sck data i/o register f-ram control 256 k x 8 f-ram array 256-byte special sector f-ram nonvolatile status register device id and serial number registers instruction decoder control logic reset logic write protect
document number: 002-19073 rev. *f page 3 of 32 preliminary CY15B102QN cy15v102qn contents pinout ................................................................................ 4 pin definitions .................................................................. 4 functional overview ........................................................ 5 memory architecture ............... .................................... 5 serial peripheral interface ( spi) bus .......................... 5 terms used in spi protocol......................................... 5 spi modes................................................................... 6 power-up to first access........ .................................... 6 functional description ..................................................... 7 command structure .................................................... 7 maximum ratings ........................................................... 19 operating range ............................................................. 19 dc electrical characteristics ........................................ 19 data retention and endurance ..................................... 20 example of an f-ram life time in an aec-q100 automotive application ...................................................................... 21 capacitance .................................................................... 22 thermal resistance ........................................................ 22 ac test conditions ........................................................ 22 ac switching characteristics ....................................... 23 power cycle timing ....................................................... 25 ordering information ...................................................... 26 ordering code definitions ...... ................................... 26 package diagram ............................................................ 27 acronyms ........................................................................ 28 document conventions ................................................. 28 units of measure ....................................................... 28 errata ............................................................................... 29 document history page ................................................. 30 sales, solutions, and legal information ...................... 32 worldwide sales and design supp ort............. .......... 32 products .................................................................... 32 psoc? solutions ...................................................... 32 cypress developer community................................. 32 technical support .................. ................................... 32
document number: 002-19073 rev. *f page 4 of 32 preliminary CY15B102QN cy15v102qn pinout figure 1. 8-pin soic pinout pin definitions pin name i/o type description cs input chip select . this active low input activates the de vice. when high, the device enters low-power standby mode, ignores other inputs, and the output is tristated. when low, the device internally activates the sck signal. a falling edge on cs must occur before every opcode. sck input serial clock . all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge of the serial clock. the clock frequency may be any value between 0 and 50 mhz and may be interrupted at any time due to its synchronous behavior . si [1] input serial input . all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet the power (i dd ) specifications. so [1] output serial output. this is the data output pin. it is driven during a read and remains tristated at all other times including when reset is low. data transitions are driven on the falling edge of the serial clock sck . wp input write protect. this active low pin prevents write operati on to the status register when wpen bit in the status register is set to ?1?. this is critical because other write protecti on features are controlled through the status register. a complete expl anation of write protection is provided in table 2 on page 9 and table 5 on page 9 . this pin has an internal weak pull-up resistor which keeps this pin high if left floating (not connected on the board). this pin can also be tied to v dd if not used. reset input hardware reset pin. this active low pin resets the device to default power on status. when reset is low, the device self-initializes and returns to the standby state. th is pin has an internal weak pull-up resistor which keeps this pin high if le ft floating (not connected on the board). this pin can also be tied to v dd if not used. v ss power supply ground for the device. must be connected to the gr ound of the system. v dd power supply power supply input to the device. si reset sck so cs wp v ss v dd top view (not to scale) 8 7 6 5 1 2 3 4 note 1. si may be connected to so for a single pin data interface.
document number: 002-19073 rev. *f page 5 of 32 preliminary CY15B102QN cy15v102qn functional overview the cy15x102qn is a serial f-ram memory. the memory array is logically organized as 262,144 8 bits and is accessed using an industry-standard serial peripheral interface (spi) bus. the functional operation of the f-ram is similar to serial flash and serial eeproms. the ma jor difference between the cy15x102qn and a serial flash or eeprom with the same pinout is the f-ram?s superio r write performance, high endurance, and low power consumption. memory architecture when accessing the cy15x102qn, the user addresses 256k locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the spi protocol, which includes a ch ip select (to permit multiple devices on the bus), an opcode, and a three-byte address. the upper six bits of the address range are ?don?t care? values. the complete address of 18 bits specifies each byte address uniquely. most functions of the cy15x102q n are either controlled by the spi interface or handled by on-board circuitry. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. th at is, the memory is read or written at the speed of the spi bus. unlike a serial flash or eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted in to the device, a write operation is complete. this is explained in more detail in the interface section. serial peripheral interface (spi) bus the cy15x102qn is an spi slave device and operates at speeds of up to 50 mhz. this high-speed serial bus provides high-performance serial communication to an spi master. many common microcontrollers have hardware spi ports allowing a direct interface. it is simple to emulate the port using ordinary port pins for microcontrollers that do not have this feature. the cy15x102qn operates in spi modes 0 and 3. spi overview the spi is a four-pin inte rface with chip select (cs ), serial input (si), serial output (so), a nd serial clock (sck) pins. the spi is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. a device on the spi bus is activated using the cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both of these modes, data is clocked into the f-ram on the rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. these opcodes specify the commands from the bus master to the slave device. after cs is activated, the first byte transferred from the bus master is the opcode. followin g the opcode, any addresses and data are then transferred. the cs must go inactive after an operation is complete and befor e a new opcode can be issued. terms used in spi protocol the commonly used terms in the spi protocol are as follows: spi master the spi master device controls the operations on the spi bus. an spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of t he slave devices using the cs pin. all of the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchroni zed with this clock. spi slave the spi slave device is activated by the master through the chip select line. a slave device gets th e sck as an input from the spi master and all the communicat ion is synchronized with this clock. an spi slave never in itiates a communication on the spi bus and acts only on the instruction from the master. the cy15x102qn operates as an spi slave and may share the spi bus with other spi slave devices. chip select ( cs ) to select any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a high-impedance state. note: a new instruction must begi n with the falling edge of cs . therefore, only one opcode can be issued for each active chip select cycle. serial clock (sck) the serial clock is generated by the spi master and the commu- nication is synchronized with this clock after cs goes low. the cy15x102qn enables spi modes 0 and 3 for data commu- nication. in both of these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefore, the first rising edge of sck signifies the arrival of the first most significant bit (msb) of an spi instruction on the si pin. further, all data inputs and outputs are synchronized with sck.
document number: 002-19073 rev. *f page 6 of 32 preliminary CY15B102QN cy15v102qn data transmission (si/so) the spi data bus consists of two lines, si and so, for serial data communication. si is also referred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the master issues instructions to t he slave through the si pin, while the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. the cy15x102qn has two separate pins for si and so, which can be connected with t he master as shown in figure 2 . for a microcontroller that has no dedicated spi bus, a general-purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the reset and wp pins. figure 3 shows such a configuration, which uses only three pins. figure 2. system configuration with spi port figure 3. system configuration without spi port most significant bit (msb) the spi protocol requires that the first bit to be transmitted is the msb. this is valid for both address and data transmission. the 2-mbit serial f-ram requires a 3-byte address for any read or write operation. because the address is only 18 bits, the first six bits, which are fed in are ignored by the device. although these six bits are ?don?t care?, cypress recommends that these bits be set to 0s to enable seamless transition to higher memory densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operation. cy15x102qn uses the standard opcodes for memory accesses. invalid opcode if an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of cs , and the so pin remains tristated. status register cy15x102qn has an 8-bit status register. the bits in the status register are used to configure the device. these bits are described in table 3 on page 9 . spi modes cy15x102qn may be driven by a microcontroller with its spi peripheral running in either of the following two modes: spi mode 0 (cpol = 0, cpha = 0) spi mode 3 (cpol = 1, cpha = 1) for both these modes, the input data is latched in on the rising edge of sck starting from the first rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge after the clock toggles is considered. the output data is available on the falling edge of sck. the two spi modes are shown in figure 4 and figure 5 . the status of the clock when the bus master is not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 the device detects the spi mode fr om the status of the sck pin when the device is selected by bringing the cs pin low. if the sck pin is low when the device is selected, spi mode 0 is assumed and if the sck pin is high, it works in spi mode 3. figure 4. spi mode 0 figure 5. spi mode 3 power-up to first access the cy15x102qn is not accessible for a t pu time after power-up. users must comply with the timing parameter, t pu , which is the minimum time from v dd (min) to the first cs low. refer to power cycle timing on page 25 for details. spi hostcontroller or spi master sck si so sck si so cs reset sck mosi miso cs1 cs2 wp1 wp2 wp cs reset wp cy15x102qn cy15x102qn spi hostcontroller or spi master sck si so cs reset p1.0 p1.1 p1.2 wp cy15x102qn 012345 67 0 1 2 3 4 5 6 7 cs sck si 012345 67 0 1 2 3 4 5 6 7 sck si cs
document number: 002-19073 rev. *f page 7 of 32 preliminary CY15B102QN cy15v102qn functional description command structure there are 15 commands, called opcodes, that can be issued by the bus master to the cy15x102qn (see ta b l e 1 ). these opcodes control the functions performed by the memory. table 1. opcode commands name description opcode hex binary write enable control wren set write enable latch 06h 0000 0110b wrdi reset write enable latch 04h 0000 0100b register access rdsr read status register 05h 0000 0101b wrsr write status register 01h 0000 0001b memory write write write memory data 02h 0000 0010b memory read read read memory data 03h 0000 0011b fstrd fast read memory data 0bh 0000 1011b special sector memory access sswr special sector write 42h 0100 0010b ssrd special sector read 4bh 0100 1011b identification and serial number rdid read device id 9fh 1001 1111b ruid read unique id 4ch 0100 1100b wrsn write serial number c2h 1100 0010b rdsn read serial number c3h 11000 011b power modes and reset dpd enter deep power-down bah 1011 1010b hbn enter hibernate mode b9h 1011 1001b reserved reserved reserved unused opcodes are reserved for future use.
document number: 002-19073 rev. *f page 8 of 32 preliminary CY15B102QN cy15v102qn write enable control commands set write enable latch (wren, 06h) the cy15x102qn will power up with writes disabled. the wren command must be issued before any write operation. sending the wren opcode allows the user to issue subsequent opcodes for write operations. thes e include writing to the status register (wrsr), the memory (write), special sector (sswr), and write serial number (wrsn). sending the wren opcode causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel = ?1? indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit - only the wren opcode can set this bit. the wel bit will be automatically cleared on the rising edge of cs following a wrdi, a wrsr, a write, a sswr, or a wrsn operation. this prevents further writes to the status register or the f-ram array without another wren command. figure 6 illustrates the wren command bus configuration. figure 6. wren bus configuration reset write enable latch (wrdi, 04h) the wrdi command disables all write activity by clearing the write enable latch. verify that th e writes are disabled by reading the wel bit in the status regist er and verify that wel is equal to ?0?. figure 7 illustrates the wrdi command bus configuration. figure 7. wrdi bus configuration 012345 67 0 1 1 0 0 0 0 0 cs sck si si hi-z opcode (06h) 012345 67 0 0 1 0 0 0 0 0 cs sck si si hi-z opcode (04h)
document number: 002-19073 rev. *f page 9 of 32 preliminary CY15B102QN cy15v102qn status register and write protection the write protection features of the cy15x1 02qn are multi-tiered and are enabled through the status register. the status regist er is organized as follows. (the default value shipped from the fa ctory for wel, bp0, bp1, bits 4?5, and wpen is ?0?, and for bit 6 is ?1?.) bits 0 and 4?5 are fixed at ?0? and bi t 6 is fixed at ?1?; none of these bits can be modified. note that bit 0 (?ready or write in progress? bit in serial flash and eeprom) is unnecessary, as the f-ram writes in real-time and is never busy, so it reads out as a ?0?. an exception to this is when the de vice is waking up either from deep power-down mode (dpd, bah) or hibernate mode (hbn, b9h) . the bp1 and bp0 control th e software write-protection features and are nonvolatile bits. the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of me mory that are write- protected as shown in ta b l e 4 . the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memo ry from writes. the remaining write protection featur es protect inadvertent changes to the block protect bits. the write protect enable bit (wpen) in the status register controls the effect of th e hardware write protect (wp ) pin. refer to figure 23 on page 24 for the wp pin timing diagram. when the wpen bit is set to ?0?, the status of the wp pin is ignored. when the wpen bit is set to ?1?, a low on the wp pin inhibits a write to the status register. thus the status register is write-protected only when wpen = ?1? and wp = ?0?. table 5 summarizes the write protection conditions. table 2. status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen (0) x (1) x (0) x (0) bp1 (0) bp0 (0) wel (0) x (0) table 3. status register bit definition bit definition description bit 0 don?t care this bit is non-writable and always returns ?0? upon read. bit 1 (wel) write enable wel indicates if the device is writ e enabled. this bit defaults to ?0? (disabled) on power-up. wel = ?1? --> write enabled wel = ?0? --> write disabled bit 2 (bp0) block protect bit ?0? used for block protection. for details, see table 4 . bit 3 (bp1) block protect bit ?1? used for block protection. for details, see table 4 . bit 4?5 don?t care these bits are non-writable and always return ?0? upon read. bit 6 don?t care this bit is non-writable and always returns ?1? upon read. bit 7 (wpen) write protect enable bit used to enable the function of write protect pin (wp ). for details, see table 5 . table 4. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 30000h to 3ffffh (upper 1/4) 1 0 20000h to 3ffffh (upper 1/2) 1 1 00000h to 3ffffh (all) table 5. write protection wel wpen wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected
document number: 002-19073 rev. *f page 10 of 32 preliminary CY15B102QN cy15v102qn register access commands read status register (rdsr, 05h) the rdsr command allows the bus master to verify the contents of the status register. reading t he status register provides information about the current state of t he write-protection features. following the rdsr opcode, the cy15x102qn will return one byte with the contents of the status register. figure 8. rdsr bus configuration write status register (wrsr, 01h) the wrsr command allows the spi bus master to write into the st atus register and change the writ e protect configuration by sett ing the wpen, bp0, and bp1 bits as required. before issuing a wrsr co mmand, the wp pin must be high or inactive. note that on the cy15x102qn, wp only prevents writing to the status register, not the memory array. before sending the wrsr command, the user must send a wren command to enable writes. executing a wrsr command is a write operation and therefore, clears the write enable latch. figure 9. wrsr bus configuration (wren not shown) 01234567 cs si sck 01234567 so 0000010 1 d7 d6 d5 d4 d3 d2 d 1 d0 hi-z hi-z msb lsb opcode (05h) read data 01234567 cs si sck 01234567 so 0000000 1 d7d6d5d4d3d2d1d0 hi-z msb lsb opcode (01h) write data
document number: 002-19073 rev. *f page 11 of 32 preliminary CY15B102QN cy15v102qn memory operation the spi interface, which is capable of a high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash and eepr oms, the cy15x102qn can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be performed. memory write operation commands write operation (write, 02h) all writes to the memory begin with a wren opcode with cs being asserted and deasserted. the next opcode is write. the write opcode is followed by a three-byte address containing the 18-bit address (a17?a0) of the first data byte to be written into the memory. the upper six bits of the three-byte address are ignored. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps cs low. if the last address of 3ffffh is reached, the internal address counter will roll over to 00000h. da ta is written on msb first. the rising edge of cs terminates a write operation. the cy15x102qn write operation is shown in figure 10 . notes: when a burst write reaches a protected block address, the automatic address increment st ops and all the subsequent data bytes received for write will be ignored by the device. eeproms use page buffers to increase their write throughput. this compensates for the technology?s inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the eighth clock). this allows any number of bytes to be written without page buffer delays. if power is lost in the middle of the write operation, only the last completed byte will be written. figure 10. memory write (wren not shown) operation 01234567 cs si sck 01234567 so 0000001 0 d7d6d5d4d3d2d1d0 hi-z hi-z msb lsb opcode (02h) write data a23 0123 4 212223 a2 2 a 2 0 a2 1 a3 a 2 a 1 a0 address 20
document number: 002-19073 rev. *f page 12 of 32 preliminary CY15B102QN cy15v102qn memory read operation commands read operation (read, 03h) after the falling edge of cs , the bus master can issue a read opcode. following the read command is a three-byte address containing the 18-bit address (a17?a0) of the first byte of the read operation. the upper six bits of the address are ignored. after the opcode and address are issued, the device drives out the read data on the next eight clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and cs is low. if the last address of 3ffffh is reached, the internal address counter will roll over to 00000h. data is read on msb first. the rising edge of cs terminates a read operation and tristates the so pin. the cy15x102qn read operation is shown in figure 11 . figure 11. memory read operation fast read operation (fast_read, 0bh) the cy15x102qn supports a fast read opcode (0bh) that is provided for opcode compatibility with serial flash devices. the fast read opcode is followed by a three-byte address containing the 18-bit address (a17?a0) of the first byte of the read operation and then a dummy byte. the dummy byte inserts a read latency of 8-clock cycle. the fast read operation is otherwise the same as an ordina ry read operation except that it requires an additional dummy byte. after receiving the opcode, address, and a dummy byte, the cy15x102qn starts driving its so line with data bytes, with msb first, and continues trans- mitting as long as the device is selected and the clock is available. in case of bulk read, the internal address counter is incremented automatically, and after the last address 3ffffh is reached, the counter rolls over to 00000h. when the device is driving data on its so line, any transition on its si line is ignored. the rising edge of cs terminates a fast read operation and tristates the so pin. the cy 15x102qn fast read operation is shown in figure 12 . note: the dummy byte can be any 8-bit value but axh (8?b1010xxxx). the lower 4 bits of axh are d on?t care bits. hence, axh essentially represents 16 different 8-bit values which shouldn't be transmitted as the dummy byte. 00h is typically used as the dummy byte in most use cases figure 12. fast read operation 01234567 cs si sck 01234567 so 0000001 1 d7 d 6 d5 d4 d3 d 2 d1 d0 hi-z hi-z msb lsb opcode (03h) read data a23 0123 4 212223 a2 2 a 2 0 a2 1 a3 a 2 a 1 a0 address 20 01234567 cs si sck 01234567 so 0000101 1 d7 d 6 d5 d4 d3 d 2 d1 d0 hi-z hi-z msb lsb opcode (0bh) read data a23 0123 4 212223 a2 2 a 2 0 a2 1 a3 a 2 a 1 a0 address msb lsb 01234567 xxxxxxxx dummy byte 20
document number: 002-19073 rev. *f page 13 of 32 preliminary CY15B102QN cy15v102qn special sector memory access commands special sector write (sswr, 42h) all writes to the 256-byte special begin with a wren opcode with cs being asserted and deasserted. the next opcode is sswr. the sswr opcode is followed by a three-byte address containing the 7-bit sector address (a6?a0) of the first data byte to be written into the special sector memory. the upper 17 bits of the three-byte address are ignored. subsequent bytes are data bytes, which are written sequentially. addresses are incre- mented internally as long as the bus master continues to issue clocks and keeps cs low. address wrap is not supported in sswr. once the internal address counter auto increments to xxx7fh, cs should toggle high to terminate the ongoing sswr operation. data is written on msb first. the rising edge of cs terminates a write operati on. the cy15x102qn special sector write operation is shown in figure 13 . notes: if power is lost in the middle of the write operation, only the last completed byte will be written. the special sector f-ram memory guarantees to retain data integrity up to three cycles of standard reflow soldering. figure 13. special sector write (wren not shown) operation special sector read (ssrd, 4bh) after the falling edge of cs , the bus master can issue an ssrd opcode. following the ssrd command is a three-byte address containing the 7-bit address (a6?a0) of the first byte of the special sector read operation. the upper 17 bits of the address are ignored. after the opcode and address are issued, the device drives out the read data on the next eight clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and cs is low. address wrap is not supported in ssrd. once the internal address counter auto increments to xxx7fh, cs should toggle high to terminate the ongoing ssrd operation. data is read on msb first. the rising edge of cs terminates a special sector read operation and tristates the so pin. the cy15x102qn special sect or read operation is shown in figure 14 . note: the special sector f-ram memory guarantees to retain data integrity up to three cycles of standard reflow soldering. figure 14. special sector read operation 01234567 cs si sck 01234567 so 0100001 0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z msb lsb opcode (42h) write data a2 3 01 2 3 4 212223 a2 2 a2 0 a2 1 a 3 a 2 a1 a0 address 20 01234567 cs si sck 01 23 45 6 7 so 0100101 1 d7 d 6 d5 d4 d3 d 2 d1 d0 hi-z hi-z msb lsb opcode (4bh) read data a23 0123 4 212223 a2 2 a 2 0 a2 1 a3 a 2 a 1 a0 address 20
document number: 002-19073 rev. *f page 14 of 32 preliminary CY15B102QN cy15v102qn identification and serial number commands read device id (rdid, 9fh) the cy15x102qn device can be interrogated for its manufac- turer, product identification, and die revision. the rdid opcode 9fh allows the user to read the 9-byte manufacturer id and product id, both of which are read-only bytes. the jedec-assigned manufacturer id places the cypress (ramtron) identifier in bank 7; t herefore, there are six bytes of the continuation code 7fh followed by the single byte c2h. there are two bytes of product id, which includes a family code, a density code, a sub code, and the product revision code. table 6 shows 9-byte device id field description. refer to ordering information on page 26 for 9-byte device id of an individual part. the cy15x102qn read device id operation is shown in figure 15 on page 14 . note: the least significant data byte (byte 0) shifts out first and the most significant data byte (byte 8) shifts out last. figure 15. read device id read unique id (ruid, 4ch) the cy15x102qn device can be interrogated for its unique id, which stores a unique number for each device. the ruid opcode 4ch allows the user to read the 8-byte unique id, which are read-only bytes. the unique id is generated by combining details on the fab lot number, wafer number, y-coordinate, and x-coordinate of the die. the cy15x102qn read unique id operation is shown in figure 16 . notes: the least significant data byte (byte 0) shifts out first and the most significant data byte (byte 7) shifts out last. the unique id registers are guaranteed to retain data integrity of up to three cycles of th e standard reflow soldering. figure 16. read unique id table 6. 9-byte device id device id field description manufacturer id [71:16] family [15:13] density [12:9] inrush [8] sub type [7:5] revision [4:3] voltage [2] frequency [1:0] 56-bit 3-bit 4-bit 1-bit 3-bit 2-bit 1-bit 2-bit 01234567 cs si sck 64 65 66 67 68 69 70 71 so 1001111 1 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z byte 0 byte 8 opcode (9fh) d7 0123 4 616263 d6 d4 d5 d3 d2 d1 d0 9-byte device id 60 msb lsb table 7. 8-byte unique id fab lot wafer no y-coordinate x-coordinate 36 bits 8 bits 10 bits 10 bits 01234567 cs si sck 56 57 58 59 60 61 62 63 so 0100110 0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z opcode (4ch) d7 0123 4 535455 d6 d4 d5 d3 d2 d1 d0 8-byte unique id 52 byte 0 byte 7 msb lsb
document number: 002-19073 rev. *f page 15 of 32 preliminary CY15B102QN cy15v102qn write serial number (wrsn, c2h) the serial number is an 8-byte one-time programmable memory space provided to the user to uniquely identify a pc board or a system. a serial number typically consists of a two-byte customer id, followed by five bytes of a unique serial number and one byte of crc check. however, the end application can define its own format for the 8-byte serial number. all writes to the serial number register begin with a wren opcode with cs being asserted and deasserted. the next opcode is wrsn. the wrsn instruction can be used in burst mode to write all the 8 bytes of serial number. after the last byte of the serial number is shifted in, cs must be driven high to complete the wrsn operation. the cy15x102qn writ e serial number operation is shown in figure 17 on page 15 . note: the crc checksum is not ca lculated by the device. the system firmware must calcul ate the crc checksum on the 7-byte content and append t he checksum to the 7-byte user-defined serial number befor e programming the 8-byte serial number into the serial number re gister. the factory default value for the 8-byte serial number is ?0000000000000000h?. figure 17. write serial numb er (wren not shown) operation read serial number (rdsn, c3h) the cy15x102qn device incorporates an 8-byte serial space provided to the user to uniquely identify the device. the serial number is read using the rdsn inst ruction. a serial number read may be performed in burst mode to read all the eight bytes at once. after the last byte of the serial number is read, the device loops back to the first (msb) byte of the serial number. an rdsn instruction can be issued by shifting the opcode for rdsn after cs goes low. the cy15x102qn read serial number operation is shown in figure 18 . note: the least significant data byte (byte 0) shifts out first and the most significant data byte (byte 7) shifts out last. figure 18. read serial number operation table 8. 8-byte serial number 16-bit customer identifier 40-bit unique number 8-bit crc sn[63:56] sn[55:48] sn[47:40] sn[39:32 ] sn[31:24] sn[23:16] sn[15:8] sn[7:0] 01234567 cs si sck so 1100001 0 d7d6d5d4d3d2d1d0 hi-z hi-z msb lsb opcode (c2h) d7 0123 4 d6 d4 d5 d3 d2 d1 d0 write 8-byte serial number 56 57 58 59 60 61 62 63 53 54 55 52 01234567 cs si sck 56 57 58 59 60 61 62 63 so 1100001 1 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z opcode (c3h) d7 0123 4 535455 d6 d4 d5 d3 d2 d1 d0 8-byte serial number 52 byte 0 byte 7 msb lsb
document number: 002-19073 rev. *f page 16 of 32 preliminary CY15B102QN cy15v102qn power modes and reset commands deep power-down mode (dpd, bah) a power-saving deep power-down mode is implemented on the cy15x102qn device. the device enters the deep power-down mode after t entdpd time after the dpd opcode bah is clocked in and a rising edge of cs is applied. when in deep-power-down mode, the sck and si pins are ignored and so will be hi-z, but the device continues to monitor the cs pin. a cs pulse-width of t csdpd or hardware reset exits the dpd mode after t extdpd time. the cs pulse-width can be generated either by sending a dummy command cycle or toggling cs alone while sck and i/os are don?t care. the i/os remain in hi-z state during the wakeup from deep power-down. refer to figure 19 for dpd entry and figure 20 for dpd exit timing. figure 19. dpd entry timing figure 20. dpd exit timing 012345 67 0 1 0 1 1 1 0 1 cs sck si so hi-z opcode (bah) enters dpd t entdpd i/os x 012 cs sck t extdpd t csdpd t su
document number: 002-19073 rev. *f page 17 of 32 preliminary CY15B102QN cy15v102qn hibernate mode (hbn, b9h) a lowest power hibernate mode is implemented on the cy15x102qn device. the device enters hibernate mode after t enthib time after the hbn opcode b9h is clocked in and a rising edge of cs is applied. when in hibernate mode, the sck and si pins are ignored and so will be hi- z, but the device continues to monitor the cs pin. on the next falling edge of cs , the device will return to normal operation within t exthib time. the so pin remains in a hi-z state during the wakeup from hibernate period. the device does not necessarily respond to an opcode within the wakeup period. to exit the hibernate mode, the controller may send a ?dummy? read, for example, and wait for the remaining t exthib time. figure 21. hibernate mode operation 012345 67 1 0 0 1 1 1 0 1 cs sck si so hi-z opcode (b9h) enters hibernate mode 012 t exthib recovers from hibernate mode t su t enthib
document number: 002-19073 rev. *f page 18 of 32 preliminary CY15B102QN cy15v102qn hardware reset function the hardware reset is an active low signal in the cy15x102qn device. when the reset pin is pulled low, the cy15x102qn self-initializes and brings its configuration setting back to the power-up status. the spi host can issue hardware reset if cy15x102qn goes into an undefined state and stops responding to any spi command. this can happen when cy15x102qn enters an internal test mode or any undefined mode either due to the wrong opcode or any glitch on the spi signals, which can internally cause latching a wrong opcode. once reset is issued, the cy15x102qn takes t reset time from reset rising edge to complete the internal reset cycle. cy15x102qn becomes inaccessible during t rec period. figure 24 on page 24 shows reset timing. endurance the cy15x102qn devices are capable of being accessed at least 10 13 times, reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an enduran ce cycle is applied on a row basis for each access (read or writ e) to the memory array. the f-ram architecture is based on an array of rows and columns of 32k rows of 64-bit each. the ent ire row is internally accessed once, whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calcu- lation. ta b l e 9 shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential 64-byte data st ream. this causes each byte to experience one endurance cycle through the loop. table 9. time to reach endurance limit for repeating 64-byte loop sck freq (mhz) endurance cycles/sec endurance cycles/year years to reach 10 13 limit 50 91,900 2.9 10 12 3.45 40 73,520 2.32 10 12 4.31 10 18,380 5.79 10 11 17.27 5 9,190 2.90 10 11 34.54
document number: 002-19073 rev. *f page 19 of 32 preliminary CY15B102QN cy15v102qn maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............................... ?55 c to + 150 c maximum accumulated storage time at 150 c ambient temperature ................................. 1000 h at 125 c ambient temperature ................................11000 h at 85 c ambient temperature ............................. 121 years maximum junction temperature ................................ 135 c supply voltage on v dd relative to v ss : cy15v102qn: ............................................ ?1.0 v to +2.4 v CY15B102QN: .............................................?1.0 v to +4.1 v input voltage ............................................ v in ? v dd + 1.0 v dc voltage applied to outputs in high-z state ................................... ?1.0 v to v dd + 1.0 v transient voltage (< 20 ns) on any pin to ground potential ........... ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) .............................. 1.0 w surface mount lead soldering temperature (3 seconds) ......................... +260 c dc output current (1 output at a time, 1s duration) ................................. 15 ma electrostatic discharge voltage human body model (jedec std jesd22-a114-b) ..... 2 kv charged device model (jedec std jesd22-c101-a) .................................... 500 v latch-up current ..................................................... >140 ma operating range device range ambient temperature v dd cy15v102qn automotive-e ?40 c to +125 c 1.71 v to 1.89 v CY15B102QN 1.8 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [2, 3] max unit v dd power supply cy15v102qn 1.71 1.8 1.89 v CY15B102QN 1.8 3.3 3.6 i dd v dd supply current v dd = 1.71 v to 1.89 v; sck toggling between v dd ? 0.2 v and v ss , other inputs v ss or v dd ? 0.2 v. so = open f sck = 1 mhz ? 0.4 1.0 ma f sck = 40 mhz ? 3.7 6.0 ma f sck = 50 mhz ? 4.5 7.0 ma v dd = 1.8 v to 3.6 v; sck toggling between v dd ? 0.2 v and vss, other inputs v ss or v dd ? 0.2 v. so = open f sck = 1 mhz ? 0.5 1.3 ma f sck = 40 mhz ? 4.3 8.0 ma f sck = 50 mhz ? 5.2 8.0 ma i sb v dd standby current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 ? c? 2.4 ?a t a = 85 ? c? ? 75a t a = 125 ? c? ? 340a v dd = 1.8 v to 3.6 v; cs = v dd . all other inputs v ss or v dd . t a = 25 ? c? 2.8 ?a t a = 85 ? c? ? 75a t a = 125 ? c? ? 350a notes 2. typical values are at 25 c, v dd = 3.3 v. 3. this parameter is guaranteed by characterization; not tested in production.
document number: 002-19073 rev. *f page 20 of 32 preliminary CY15B102QN cy15v102qn i dpd deep power-down current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 ? c ? 0.70 ? a t a = 85 ? c? ? 15a t a = 125 ? c? ? 70a v dd = 1.8 v to 3.6 v; cs = v dd . all other inputs v ss or v dd . t a = 25 ? c? 1.0 ?a t a = 85 ? c? ? 17a t a = 125 ? c? ? 80a i hbn hibernate mode current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 ? c? 0.1 ?a t a = 85 ? c? ? 0.9a t a = 125 ? c? ? 8.0a v dd = 1.8 v to 3.6 v; cs = v dd . all other inputs v ss or v dd . t a = 25 ? c? 0.1 ?a t a = 85 ? c? ? 1.6a t a = 125 ? c? ? 14a i li input leakage current on i/o pins except wp and reset pins v ss < v in < v dd ?1 ? 5 a input leakage current on wp and reset pins ?100 ? 5 a i lo output leakage current v ss < v out < v dd ?5 ? 5 ? a v ih input high voltage 0.7 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.3 v dd v v oh1 output high voltage i oh = ?1 ma, v dd = 2.7 v 2.4 ? ? v v oh2 output high voltage i oh = ?100 ? av dd ? 0.2 ? ? v v ol1 output low voltage i ol = 2 ma, v dd = 2.7 v ? ? 0.4 v v ol2 output low voltage i ol = 150 ? a??0.2v dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [2, 3] max unit data retention and endurance parameter description test condition min max unit t dr data retention t a = 125 ? c 11000 ? hours t a = 105 ? c11?years t a = 85 ? c121? nv c endurance over operating temperature 10 13 ? cycles
document number: 002-19073 rev. *f page 21 of 32 preliminary CY15B102QN cy15v102qn example of an f-ra m life time in an aec-q100 automotive application an application does not operate under a steady temperature for t he entire usage life time of the application. instead, it is of ten expected to operate in multiple temperature enviro nments throughout the application?s usage life time. accordingly, the retention specif ication for f-ram in applications often needs to be calculated cumulati vely. an example calculation for a multi-temperature thermal pro file is given in the following table. temperature t time factor t acceleration factor with respect to tmax a [4] profile factor p profile life time l (p) t1 = 125 ? c t1 = 0.1 a1 = 1 8.33 > 10.46 years t2 = 105 ? c t2 = 0.15 a2 = 8.67 t3 = 85 ? c t3 = 0.25 a3 = 95.68 t4 = 55 ? c t4 = 0.50 a4 = 6074.80 a lt ?? ltmax ?? ------------------------ e ea k ------- 1 t --- 1 tmax --------------- - ? ?? ?? == p 1 t1 a1 ------- t2 a2 ------- t3 a3 ------- t4 a4 ------- +++ ?? ?? ------------------------------------------------------- - = lp ?? pltmax ?? ? = note 4. where k is the boltzmann constant 8.617 10 -5 ev/k, tmax is the highest temperatur e specified for the product, and t is any temperature within the f-ram product specification. all temperatures are in kelvin in the equation.
document number: 002-19073 rev. *f page 22 of 32 preliminary CY15B102QN cy15v102qn ac test conditions input pulse levels ................................ 10% and 90% of v dd input rise and fall times .................................................. 3 ns input and output timing reference levels ............... 0.5 v dd output load capacitance ............................................. 30 pf capacitance for all packages. parameter [5] description test conditions max unit c o output pin capacitance (so) t a = 25 c, f = 1 mhz, v dd = 3.3 v 8 pf c i input pin capacitance 6pf thermal resistance parameter [5] description test conditions 8-pin soic package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 88.6 ? c/w ? jc thermal resistance (junction to case) 56 ? c/w note 5. this parameter is guaranteed by c haracterization; not tested in production.
document number: 002-19073 rev. *f page 23 of 32 preliminary CY15B102QN cy15v102qn ac switching characteristics over the operating range parameters [6] description 40 mhz 50 mhz unit cypress parameter alt. parameter min max min max f sck ? sck clock frequency 0 40 0 50 mhz t ch ? clock high time 11 ? 9 ? ns t cl ? clock low time 11 ? 9 ? ns t css t csu chip select setup 5 ? 5 ? ns t csh t csh chip select hold 5 ? 5 ? ns t hzcs t od [ 7 , 8] output disable time ? 12 ? 10 ns t co t odv output data valid time ? 9 ? 8 ns t oh ? output hold time 1 ? 1 ? ns t cs t d deselect time 40 ? 40 ? ns t sd t su data setup time 5 ? 5 ? ns t hd t h data hold time 5 ? 5 ? ns t wps t whsl wp setup time (w.r.t cs ) 20 ? 20 ? ns t wph t shwl wp hold time (w.r.t cs ) 20 ? 20 ? ns t reset [9] ? reset execute time 450 ? 450 ? s t rp t rlrh reset pulse width 200 ? 200 ? ns notes 6. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , and output loading of the specified i ol /i oh and 30-pf load capacitance shown in ac test conditions on page 22 . 7. t hzcs is specified with a load capacitance of 5 pf. transiti on is measured when the output enters a high-impedance state. 8. this parameter is guaranteed by charac terization; not tested in production. 9. time to complete the reset routine and ready to accept the command.
document number: 002-19073 rev. *f page 24 of 32 preliminary CY15B102QN cy15v102qn figure 22. synchronous data timing (mode 0) figure 23. write protect timing during write status register (wrsr) operation figure 24. hardware reset ac timing cs sck si t cs t csh t oh t hzcs t co t clz t hd t sd t css t ch t cl so valid data in data out hi-z hi-z x x x x t wps 01234567 cs si sck 01234567 so 0000000 1 d7d6 d5 d4d3d2d1 d0 hi-z msb lsb opcode (01h) write data t wph cs reset t rp t reset t reset t rp reset new reset
document number: 002-19073 rev. *f page 25 of 32 preliminary CY15B102QN cy15v102qn figure 25. power cycle timing power cycle timing over the operating range parameter [10] description min max unit cypress parameter alt. parameter t pu power-up v dd (min) to first access (cs low) 450 ? s t vr [11] v dd power-up ramp rate 30 ? s/v t vf [11] v dd power-down ramp rate 20 ? s/v t entdpd [ 12 ] t dp cs high to enter deep power-down (cs high to hibernate mode current) ? 3 s t csdpd cs pulse width to wake up from deep power-down mode 0.015 2.0 s t extdpd [ 12 ] t rdp recovery time from deep power-down mode (cs low to ready for access) ? 10 s t enthib [ 13 ] time to enter hibernate (cs high to enter hibernate) ? 3 s t exthib [ 13 ] t rec recovery time from hibernate mode (cs low to ready for access) ? 450 s v dd (low) low v dd where initialization must occur 0.6 ? v t pd v dd (low) time when v dd (low) at 0.6 v 130 ? s v dd (low) time when v dd (low) at v ss 70 ? s v dd t pu v dd (min) v dd (max) t vr time device access allowed t vf v dd t pu v dd (min) v dd (max) t vr t pd v dd (low) no device access allowed device access allowed time notes 10. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , and output loading of the specified i ol /i oh and 30-pf load capacitance shown in ac test conditions on page 22 . 11. slope measured at any point on the v dd waveform. 12. guaranteed by design. refer to figure 19 on page 16 for deep sleep mode recovery timing. 13. guaranteed by design. refer to figure 21 on page 17 for hibernate mode recovery timing.
document number: 002-19073 rev. *f page 26 of 32 preliminary CY15B102QN cy15v102qn all these parts are pb-free. contact your local cypre ss sales representative for av ailability of these parts. ordering code definitions ordering information ordering code device id package diagram package type operating range cy15v102qn-50sxees 7f7f7f7f7f7fc22a64 001-85261 8-pin soic (eiaj) automotive-e cy 15 b 102 q - 50 s x e t options: es = engineering sample ; blank = standard; t = tape and reel temperature range: e = automotive-e (-40 c to +125 c) x = pb-free package type: s = 8-pin soic (eiaj) frequency: 50 = 50 mhz cy = cypress 15 = f-ram voltage: v = 1.71 v to 1.89 v (1.8 v typical ) b = 1.8 v to 3.6 v (3.3 v typical ) density: 102 = 2-mbit interface: q = spi f-ram n n = no inrush current control
document number: 002-19073 rev. *f page 27 of 32 preliminary CY15B102QN cy15v102qn package diagram figure 26. 8-pin soic (208 mils) package outline, 001-85261 001-85261 **
document number: 002-19073 rev. *f page 28 of 32 preliminary CY15B102QN cy15v102qn acronyms document conventions units of measure acronym description cpha clock phase cpol clock polarity eeprom electrically erasable programmable read-only memory eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit rohs restriction of hazardous substances spi serial peripheral interface soic small outline integrated circuit gqfn grid array flat no-lead symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mbit megabit mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond wohm % percent pf picofarad vvolt wwatt
document number: 002-19073 rev. *f page 29 of 32 preliminary CY15B102QN cy15v102qn errata this section describes the errata for the excelon-auto, automoti ve-e 2-mb spi f-ram product. details include errata trigger con di- tions, scope of impact, available workarounds, and silicon revisi on applicability. compare this document with the device's data sheet for a complete functional description. contact your local cypress sales re presentative if you have questions. part numbers affected qualification status sampling (engineering samples) errata summary the following table defines the errata applicability to cy15v102qn engineering samples. note: errata items in the following table are hyperlinked. click on any item entry to jump to its description. part number device characteristics cy15v102qn-50sxees 8-mbit (1024k 8) se rial peripheral interface (spi) f-ram, 1.71 v to 1.89 v (1.8-v typical), automotive-e (?40 oc to +125 oc) temperature items part number silicon revision fix status [1.] dc parameters measure higher than the datasheet specifications. cy15v102qn-50sxees ** this issue will be fixed in production silicon. 1. dc parameters measure higher than the datasheet specifications. problem definition some dc parameters exceed datasheet (rev. *f) specification limits. refer to table 10 for details. parameters affected refer to ta b l e 1 0 for details. trigger condition(s) measured against specified test conditions in the datasheet. scope of impact dc currents measure higher than the spec. workaround none fix status this issue will be fixed in production silicon. table 10. cy15v102qn datasheet specifications vs engineering sample measurement parameter description test conditions datasheet (rev *f) measurement on sample (**si) unit min typ max min typ max i sb v dd standby current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc ? 2.4 ? ? 262 ? a t a = 85 oc ? ? 75 ? ? 287 a t a = 125 oc ? ? 340 ? ? 610 a i dpd deep-power down current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc ? 0.70 ? ? 261 ? a t a = 85 oc ? ? 15 ? ? 265 a t a = 125 oc ? ? 17 ? ? 280 a
document number: 002-19073 rev. *f page 30 of 32 preliminary CY15B102QN cy15v102qn document history page document title: CY15B102QN/cy15v102qn, excelon?-auto 2-mbit (256k 8) auto motive-e serial (spi) f-ram document number: 002-19073 rev. ecn no. orig. of change submission date description of change ** 5658409 zsk 03/14/2017 new data sheet. *a 5667997 zsk 03/22/2017 updated features : updated values under ?low-power consumption?. updated dc electrical characteristics : updated values corresponding to i dd , i sb , i dpd , i hbn parameters. *b 5783777 zsk 06/23/2017 updated document ti tle to read as ?CY15B102QN/cy15v102qn, 2-mbit (256k 8) automotive-e serial (spi) f-ram?. changed status from advance to preliminary. replaced cy15b102q with CY15B102QN in all instances across the document. replaced cy15v102q with cy15v102qn in all instances across the document. replaced cy15x102q with cy15x102qn in all instances across the document. updated features : updated values under ?low-power consumption?. updated pinout : updated figure 1 . updated pin definitions : updated details in ?description? column corresponding to wp and reset pins. updated functional overview : updated memory architecture : updated description. updated terms used in spi protocol : updated data transmission (si/so) (updated figure 2 , and figure 3 ). updated most significant bit (msb) (updated description). updated functional description : updated command structure : updated ta b l e 1 . updated memory operation (updated description). updated memory write operation commands (updated description). updated memory read operation commands (updated description). updated special sector memory access commands (updated description). updated identification and serial number commands (updated description; and also updated table 6 ). updated power modes and reset commands (updated description; and also updated figure 19 , and figure 21 and added figure 20 ). updated dc electrical characteristics : updated values corresponding to i sb and i dpd parameters. updated details in ?description?, ?min? and ?max? columns corresponding to i li parameter. updated details in ?min? and ?max? columns corresponding to i lo parameter. updated thermal resistance : replaced ?qfn? with ?soic? in column heading and updated all values in that column. updated ac switching characteristics : changed maximum value of t co parameter from 7 ns to 8 ns. updated power cycle timing : updated details corresponding to t entdpd , t extdpd , t enthib , t exithib and t pd parameters. added t csdpd , v dd (low) parameters and thei r corresponding details. updated figure 25 . updated ordering information : updated part numbers. added a column ?device id? and added details in that column. updated ordering code definitions .
document number: 002-19073 rev. *f page 31 of 32 preliminary CY15B102QN cy15v102qn *c 5891073 zsk 09/21/2017 updated functional description : updated command structure : updated power modes and reset commands (updated description). updated ac switching characteristics : removed t rs , t rh parameters and their corresponding details. added t reset parameter and its corresponding details. updated figure 24 . *d 5942634 zsk 11/02/2017 updated features : updated values under ?low-power consumption?. updated ordering information : updated part numbers. updated ordering code definitions . *e 5983131 zsk 12/04/2017 updated ordering information : no change in part numbers. replaced ?7f7f7f7f7f7fc22c64? with ?7f7f7f7f7f7fc22a64? in ?device id? column. *f 6044990 zsk 01/25/2018 updated the datasheet title. added 50 mhz frequency range related information in all instances across the document. updated features : updated values under ?low-power consumption?. updated functional overview : updated serial peripheral interface (spi) bus : updated description. updated functional description : updated command structure : updated power modes and reset commands (updated ta b l e 9 ). updated dc electrical characteristics : updated details corresponding to i dd , i sb , i dpd , and i hbn parameters. updated note 2. updated capacitance : updated details in ?test conditions? column. updated ac switching characteristics : updated values corresponding to f sck , t ch , t cl , t hzcs , and t co parameters. added errata . updated to new template. document history page (continued) document title: CY15B102QN/cy15v102qn, excelon?-auto 2-mbit (256k 8) auto motive-e serial (spi) f-ram document number: 002-19073 rev. ecn no. orig. of change submission date description of change
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